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Pseudowire/Circuit Emulation IP Cores

Arrive’s FPGA-based Pseudowire/Circuit Emulation IP Cores offer a family of complete solutions for pseudowire and mobile backhaul applications.

Arrive Psuedowire/Circuit Emulation IP Cores provide total solutions in groupings of 1 to 16 DS1/E1/J1 or 1 to 32 DS1/E1/J1 lines; aggregation nodes with up to 84/63 DS1/E1 lines; high-density nodes with 336/252 DS1/E1 lines; or very dense nodes with 1344/1008 DS1/E1/J1 lines. The aggregation and higher density nodes use SONET/SDH interfaces for the service side connection.

Arrive’s IP Cores are provided in fully complete bitstream or encrypted netlist format along with firmware device driver/software API packages, BSP, schematic and layout reference design files, design reviews, board testing and support from initial project definition to mass production. The IP Core bitstreams and encrypted netlists are targeted to specific FPGA devices that are selected based on the mix of features requested and customer preference.

 

All IP Cores are provided with Arrive's SDK with a single API software driver that supports protocol stack handling. For customers who want to maximize investment on existing software, Arrive supports integration of its SDK into a customer's existing software.  SDK source code and full documentation is provided.

The Pseudowire IP Core family begins with a series of core features. From these, each specific design is tailored to a customer’s specifications.

Sample IP Cores

Other Pseudowire IP Cores and higher speed variants are available.  Please contact us for more information.