4xSTM-1/OC-3 Pseudowire CodeChips

CodeChip AF6-4STM1 -ATM/IMA AF6-4STM1 -PPP/MLPPP AF6-4STM1-CEP AF6-4STM1-CES
Feature ATM/IMA/ATM PW HDLC/PPP/MLPPP 252/336 SONET/SDH PW 252/336 E1/DS1 PW
Capacity Throughput 4 STM-1 4 STM-1 4 STM-1 4 STM-1
PW connections Up to 1024 Up to 1024 Up to 252/336 Up to 252/336
DS1/E1 Channels 336/252 336/252
System Side Interfaces SONET/SDH 1xOC-12/STM-4 or 4xOC-3/STM-1 1xOC-12/STM-4 or 4xOC-3/STM-1 1xOC-12/STM-4 or 4xOC-3/STM-1 1xOC-12/STM-4 or 4xOC-3/STM-1
Protection SW-Based MSP 1+1, other optional SW-Based MSP 1+1, other optional SW-Based MSP 1+1, other optional SW-Based MSP 1+1, other optional
APS Speed < 50ms < 50ms < 50ms < 50ms
Client Side Interfaces GbE 2xGbE: One active and one standby 2xGbE: One active and one standby 2xGbE: One active and one standby 2xGbE: One active and one standby
PSN Ethernet/MPLS/IP Yes Yes Yes Yes
Circuits PDH PW Yes Yes
SONET/SDH PW Yes
ATM PW Yes
HCLC/PPP/MLPPP PW Yes
ATM IMA/ATM SW Yes
Max number links 336
Max number groups 168
Links/Groups 32
Delay compensation 256ms
MLPPP Links 336
Bundles 168
Links/bundle 16
Classes/bundle 16
Delay compensation 100ms
Circuit Interface External Memory 5×16-bit DDR2*/3 4×16-bit DDR2*/3 4×16-bit DDR2*/3
PDH Timing LoopTime/External ACR/DCR/LoopTime/External LoopTime/External ACR/DCR/LoopTime/External
CEP Timing APM and EPAR
Availability Now Now Now Now

*Note: Support of DDR2 or DDR3 depends on the specific FPGA selection. Customers should consult with Arrive about this.

 

Higher Bandwidth Pseudowire CodeChips

CodeChip AF6-8STM1-CES/CEP AF6-16STM1-CES/CEP
Feature 252/336 E1/DS1 PW
CEP (RFC4842)
VC11, VC12; VC-3, VC-4 (both Basic and Fractional)
504/672 E1/DS1 PW
CEP (RFC4842)
VC11, VC12; VC-3, VC-4 (both Basic and Fractional)
Capacity Throughput 4 STM-1 8 STM-1
PW connections 672/504SAToP, 1024 CESoPSN 672/504SAToP, 1024 CESoPSN
DS1/E1 Channels 672 DS1 or 504 E1 672 DS1 or 504 E1
System Side Interfaces SONET/SDH 8xOC-3/STM-1 ports with/without 1+1 APS (8xSTM-1 throughput) 16xOC-3/STM-1 ports with/without 1+1 APS (8xSTM-1 throughput)
Protection PORT {Linear, 1+1(P-to-P, UPSR)}
UNIT {Linear, 1+1(P-to-P, UPSR)} (option)
PORT {Linear, 1+1(P-to-P, UPSR)}
UNIT {Linear, 1+1(P-to-P, UPSR)} (option)
APS Speed < 50ms < 50ms
Client Side Interfaces GbE 4xGbE: One active and one standby 8xGbE: One active and one standby
PSN Ethernet/MPLS/IP Yes Yes
Circuits PDH PW Yes Yes
SONET/SDH PW Yes Yes
ATM PW Available Available
HCLC/PPP/MLPPP PW Available Available
ATM IMA/ATM SW
Max number links
Max number groups
Links/Groups
Delay compensation
MLPPP Links
Bundles
Links/bundle
Classes/bundle
Delay compensation
Circuit Interface External Memory  16-bit DDR2*/3 16-bit DDR2*/3
PDH Timing ACR/DCR/LoopTime/External. 64xACR/DCR clock recovery algorithm for SAToP, CESoPSN ACR/DCR/LoopTime/External. 64xACR/DCR clock recovery algorithm for SAToP, CESoPSN
CEP Timing APM and EPAR APM and EPAR
Availability Now Now

*Note: Support of DDR2 or DDR3 depends on the specific FPGA selection. Customers should consult with Arrive about this.