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Pseudowire / Circuit Emulation |
Pseudowires (PW) are a way to emulate a native
service (e.g. PDH, SONET) over a Packet Switched
Network (PSN). The pseudowire is used to re-create,
as far as possible, the properties of a single
passive wire that can carry the native service
traffic.
Circuit Emulation (CE) is a sub-set of Pseudowire
technology that is specifically aimed at making PSN
networks look like a collection of private circuits.
Typically the circuits being emulated are of the
T1/E1 type.
Arrives Thalassa platform offers a flexible FPGA
based solution for all your PW or CE needs.
Customers can select their exact solution needs from
a wide range of functions and interfaces and receive
a fully verified solution mapped to the FPGA of
their choice. This approach offers unbeatable time
to market advantages as well as freeing up precious
internal R&D resources. Additionally, Thalassa can
be combined with Arrive’s other product offerings
(AT4848 Family, AT2450) to deliver powerful
one stop internetworking solutions.
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|
|
AT6620 |
AT6552 |
AT6330 |
|
|
Features |
Small PDH TDM and Packet/Cell
Pseudowire Emulation over PSN |
High PDH TDM and Packet/Cell
Pseudowire Emulation over PSN |
CEP SONET/SDH Pseudowire Emulation over
PSN |
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|
Target FPGA Family |
Altera Cyclone |
Altera |
Altera |
|
Capacity |
Maximum Throughput |
311M |
2G |
622M |
|
Channel |
256 |
512 |
336 |
|
DS0 |
1024 (32 E1s) |
8192/16384 (256/512 E1s) |
None |
|
PSN |
Ethernet/MPLS/IP |
Yes |
Yes |
Yes |
|
Circuits |
DS3/E3/DS1/E1 SAToP |
Yes |
Yes |
None |
|
DS1/E1 CESoPSN/TDMoIP |
Yes |
Yes |
None |
|
NxDS0 CESoPSN/TDMoIP |
Yes |
Yes |
None |
|
STS-1 |
None |
None |
Yes |
|
VT/TU |
None |
None |
Yes |
|
ATM |
Yes |
Yes |
None |
|
HDLC |
Yes |
Yes |
None |
|
PPP |
Yes |
Yes |
None |
|
FR |
Yes |
Yes |
None |
|
Ethernet |
Yes |
Yes |
None |
|
Circuit Interface |
Serial DS3/E3 |
1 |
1 |
None |
|
Serial DS1/E1 |
32 |
32 |
None |
|
AT PDH Bus |
Yes |
Yes |
None |
|
AT DS0 Bus |
Yes |
Yes |
None |
|
H.110/H-MVIP/ST-Bus |
8 |
8 |
None |
|
HSSI Like |
1 |
1 |
None |
|
V.35 Like |
8 |
8 |
None |
|
SPI-3 |
1 |
|
None |
|
OC-N/STM-N |
None |
None |
OC-12/STM-4 |
|
Packet Interface |
Parallel GMII (GE) |
1 |
|
1 |
|
Serial MII (FE) |
4 |
8 |
8 |
|
SPI-3 |
1 |
1 |
1 |
|
Optional Functions |
PDH Framer |
Yes |
Yes |
None |
|
MAC |
Yes |
Yes |
Yes |
|
PDH VCAT/LCAS |
Yes |
None |
None |
|
ATM/HDLC Encapsulation |
Yes |
Yes |
None |
|
RAM |
|
DDR2 |
DDR2 |
DDR2 |
For more
details please refer to Thalassa platform
Short Form Datasheet
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