Arrive Technologies’ Calypso is a family of complete Carrier Ethernet System-on-a-Chip devices. Calypso can also include optional Pseudowire support, based on Arrive Technologies’ proven Thalassa product line. Calypso offers Packet Processing, Switch, and Flow Processors targeted with different capacities, I/O, features and cost to meet the varied needs of equipment suppliers.
Timing methods such as IEEE1588v2, and G.8262/Y.1362 Synchronous Ethernet (SyncE) are supported. If Pseudowire support is added, ACR (Adaptive Clock Recovery) and DCR (Differential Clock Recovery) are available.
Calypso Supports MEF E-LAN, E-Line, E-Tree, and PWE (SAToP, CESoP, ATM/IMA, MLPPP) services. OAM methods such as IEEE 802.1ag CFM (Connectivity Fault Management), IEEE 802.3ah EFM (Ethernet in the First Mile), and ITU-T Recommendation Y.1731 are supported. Redundancy features such as Ethernet link aggregation (IEEE 802.3ad), Spanning tree (STP) (IEEE 802.1D, IEEE 802.1w, IEEE 802.1s), Rapid spanning tree (RSTP), Ethernet Linear Protection Switching 1+1, 1:1 (G.8031), Ethernet Ring Protection Switching (G.8032), and MPLS 1+1, 1:1 protection are supported.
Calypso can be used on various packet system line cards and pizza-box systems for optical packet transport and packet radio transport. Broad Applications include wireline networks and wireless networks. Many specific applications are possible, such as WDM-PON, FTTH, wholesale Ethernet, LTE, 3G and 4G backhaul, microwave radio backhaul, eNodeB and RT.
CoreDesigns
Calypso is implemented in Field Programmable Gate Arrays (FPGAs) for easy field upgrades, configuration, and standards updates. The Calypso FPGA approach assures compliance with changes to technology standards and it facilitates a shortened time-to-market. It also allows for product differentiation, because customers sometimes include their own logic in the same FPGA (by coordinating with Arrive's design team). Arrive Technologies is able to support this as part of the design process. Some customers prefer to provide a list of relevant FPGAs already in their purchasing system, and ask which part numbers and packages could fit the design. Arrive Technologies has the flexibility to help with these goals as well.
The Calypso family begins with three core designs. These cores are known as CK2. From these, each customer's specific design is tailored to specifications that are mutually agreed upon. A suitable FPGA vendor, part number and package are agreed upon also. A specific AF5xxxxx device is then designed and tested. Each Calypso design is customized on agreement with user requirements and price is quoted per application.
Calypso Core – CK2-04
Optimized for Packet Microwave Radio, eNodeB, RT, IDU, ODU or ODR.
Switching capacity of 4 Gbps – 5 Gbps.
Three to five Gigabit Ethernet ports that include integrated CDRs, allowing simple connection to SFP modules.
2x 10/100 Mbps Ethernet ports.
Supports hardware-based Link OAM and CFM OAM.
Supports IEEE1588v2 and SyncE clocking methods.
Calypso Core – CK2-40
Optimized for 40Gbps (or COT).
Switching capacity of 20 Gbps – 44 Gbps.
One or two 10GbE ports that allow connections to XAUI modules, or direct serial connections to 10G modules.
Up to 24x GbE ports.
Supports hardware-based Link OAM and CFM OAM.
Supports IEEE1588v2 and SyncE clocking methods.
Optional support for Pseudowires in Calypso
Calypso designs based on CK2-04 or CK2-40 core designs can optionally include:
Up to 16x E1/T1/J1 ports (LIU ports).
Up to 16x SAToP TDM channels.
ACR and DCR PDH clock recovery methods.
Calypso Core – CK2-04 IMA
CK2-04 IMA is a CK2-04 core with additional Pseudowire support. However, in addition it includes more than just 1-16 SAToP channels. The designation “IMA” is just a shortened way of saying that more comprehensive pseudowire support is included. With this design core as a basis, CESoPSN is available in addition to SAToP PWE support. Also, ATM/IMA and MLPPP are available for transport of data channels over Pseudowires. These features are often used in Mobile Backhaul applications.
If even more Pseudowire support is needed, such as higher channel counts or larger numbers of Pseudowires, a Calypso design can be combined with a larger Thalassa design.
Optimized for Packet Microwave Radio, eNodeB, RT, IDU, ODU or ODR.
Switching capacity of 4 Gbps – 5 Gbps.
Three to five Gigabit Ethernet ports that include integrated CDRs, allowing simple connection to SFP modules.
2x 10/100 Mbps Ethernet ports.
Up to 16x E1/T1/J1 ports (LIU ports).
Supports hardware-based Link OAM and CFM OAM.
Supports IEEE1588v2 and SyncE clocking methods.
Up to 16x SAToP or CESoP TDM channels.
16x DS1/E1 pseudowires of IMA/ATM.
16x DS1/E1 pseudowires of MLPPP.
SDK (Software Development Kit)
A single software development kit is offered for the CK2/Calypso family. It is compliant to ANSI-C, platform independent via a Hardware Abstraction Layer (HAL) module, and Operating System independent via an Operating System Abstraction Layer (OSAL) module. The SDK is intended to relieve the system software developer of the task of recreating CALYPSO device drivers, in order to speed up the system development and ensure a quick transition to production.
Evaluation Platforms
Evaluation platforms are available. These platforms are designed to allow prospective customers to comprehensively test and evaluate Arrive's solutions and for existing customers to develop applications prior to their own hardware becoming available.
The SDK (Software Development Kit) is also used for evaluation and/or demonstration purposes. Text scripts are provided for specific configurations. Evaluation and testing can be controlled via a 10/100BT Ethernet port, which is connected to the onboard MPC8272 by either a PC or a LAN. A standard RS-232 debugging port is also provided.
Contact
sales@arrivetechnologies.com for documentation, technical information and pricing information.
