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Highly-Integrated OC-48/STM-16 Add/Drop Multiplexer On A Chip

JULY 4, 2005 - The AT4848 is a highly integrated OC-48/STM-16 or OC-12/STM-4 Multiservice Add/Drop Multiplexer (ADM) on a chip. It provides OC-48/12/03/EC-1 and the full range of PDH and Data interfaces. The device can be used in many next generation data over SONET/SDH systems including Multiservice Provisioning Platforms (MSPP) and many access & enterprise equipment with integrated MS-ADM. Due to its high integration, broad functionality and low cost, it can be used from a complex mapper, flexible ring interface, micro-MSPP to a full MS-ADM/MSPP.

The AT4848 has integrated cross connects supporting DS0, VT/TU and STS level switching. The device includes MACs or framers for a full range of drop side interfaces including Fast Ethernet, Gigabit Ethernet, storage and video protocols, SONET/SDH and high density DS1/E1s and DS3/E3 with M13 multiplexing. The AT4848 supports Frame and Transparent GFP mapping, HI and LO virtual concatenation (VCAT) and LCAS with 128 groups.

The AT4848 provides RPR over SONET/SDH and VLAN/MPLS applications with on-chip L2 Aggregation & Management and RPR MAC. An OIF SPI interface is available for broad functional expansion through an external network processor, additional Ethernet MACs or additional RPR MAC.

The AT4848 product will include the chip, a micro-ADM evaluation board, driver, application, test and debugging software.

The AT4848 has complete set of SONET/SDH capabilities in contrast to other devices on the market. The key areas where the AT4848 surpasses these other devices fall into these areas:

• Supports 4 Fiber OC-48 or OC-12 network interfaces under software control
• Provides a full VT/TU & STS/VC cross-connect not simple assigners
• Provides a flexible aggregation engine on the Ethernet ports for VLAN/MPLS with classifying, policing, queuing, shaping and scheduling
• Provides high density 336DS1/252E1 and 12DS3 PDH framers with M13 multiplexing and mapping
• Offers an SPI port for future NP L2+ and L3 processing and expansion
• Supports RPR, BLSR, UPSR/SNCP Rings
• Provides drop side OC-12/OC-3/EC-1 interfaces
• Provides RPR MAC controller
• Provides Stratum 3 Synchronization system
• Provides support for GFP-F/T and SAN interfaces FC, FICON and ESCON and video DVB-ASI
• Supports HI or LO LCAS and 128 VCGs

analogZONE Says . . .

I had to think twice about reviewing Arrive Technologies' AT4848 multi-service OC-48 ADM/Framer/Mapper because it's a very ambitious chip being produced by a new company without a track record. I'm especially cautious since I'd not even heard of the company until Tom Eames, their CSO (Chief Strategic Officer -- a new term for me) approached me a couple of weeks ago as they prepared to emerge from semi-stealth mode. I use the term "ambitious" here because Arrive's part appears to offer levels of speed and functionality that leapfrog the efforts of the major SONET players such as Agere, Galazar, PMC-Sierra, and Transwitch, as well as upstarts like Crimson, Parama, and Raza.

All that being said, my conversations with Eames convinced me that Arrive was not the prototypical scam startup that comes to market with little more than a couple of Stanford PhDs, a PR team, and a stack of pretty PowerPoint slides. Some of this assurance came from the fact that much of the Arrive team was from the original team that started Optilink, the company that gave birth to the first OC-3 DLCs, and spun off Calix, Next Level, AFC, and Cerent. While Optilink and the others are box, not chip makers, many of these ventures produced their own successful SONET ASICs in the process. This, and the sensible way the Arrive design team approached its formidable project, were enough to let me believe that their chip thing had enough of a chance of working that I'd write it up and let you judge for yourself.

But before we begin in earnest, please note that my review of the AT4848 came together so far ahead of the normal PR cycle that Arrive did not have the usual press release and "dog-and-pony" PowerPoint slide show ready, so we had to improvise. In lieu of the usual fluffy press release, I've posted a pithy description of the chip that's cribbed from their product brief. Besides sparing you the excess verbiage, getting all the specs out of the way allows me to confine my review to some technical and market analysis.

The AT4848 is formidable in both its speed and its ability to do high and low-order mapping for the widest range of networking protocols I can recall. It adds mapping for GbE, SAN, all PDH (DS0-DS1, E1/3, etc), high and low-order LCAS, to the basic framing and cross-connect ADM-like functions done by the likes of Parama and Crimson. A quick look at the three add/drop sections on the chip (see the Fig.) will give you a good idea of how versatile the AT4848 really is.

The mapper's VCAT/LCAS processor supports 128 VCGs with up to 32 10/100 Ethernet streams per VCG. It feeds eight 10/100 ports and 2 GbE (or FICON) ports which only need a PHY chip and magnetics to get you networked. A SPI-3 expansion port lets you add more Ethernet ports, do some layer-3 processing, or even support a second RPR MAC. Since the LAN-side port's capacity exceeds the OC-48 line side capacity, Arrive has built in some intelligent over-subscription mechanisms that allow each stream in a VCAT channel to be assigned one of 256 levels of priority queuing.

While there are several excellent multi-service framer/mapper products on the market that have significant subsets of the functionality offered by Arrive (Agere, Galazar, PMC, and Raza come to mind), they all run at OC-3/OC-12 speeds versus Arrive's OC-48 capacity. Delivering MSPP capabilities at OC-48 speeds is at the core of their strategy which tightly targets the multi-service market. They believe that 2.5 Gbit/s will be the minimum bandwidth requirement for a commercially-viable MSPP to be packing within the next year or so. They base this on recent industry analysis which indicates that in order to support a typical load of 500 subscribers with real triple play an MSPP will have to be provisioned at well over OC-12.

OC-48 capability is also important because it enables a carrier to split off OC-12 and OC-3 rings to serve outlying areas, provide aggregation infrastructures, or even provide high-capacity access rings for an individual large customer. To this end the AT4848's SONET/SDH add/drop port is equipped with a framer that lets you hang nearly any combination of OC- or STM- connections off of it.

The other leg of their strategy is to lower the cost of simultaneous support for VCAT-based EoS and PDH-based legacy services. This capability is critical for large, established, carriers who need to migrate their customer base to all-IP services in a gradual, controlled manner. That's why their chip supports such a large number of DS-1 and DS-3 connections. Rather than building 336 DS-1 framers, Arrive actually built a single multiplexed framer engine that supports all the channels, something that saves lots of real estate and power. A similar approach was used to implement most other multi-channel functions on the chip.

While I'll let you peruse the manufacturer's specs for all the details, the AT4848 packs a few other clever features worth noting here. For example, the chip includes most of the elements of a stratum-3 clock synthesizer (it just requires an external DAC) required to extract an 8 kHz timing references from a SONET line or timing distribution network. The timing circuit is very telco-friendly, can make a hitless transition to its internal source in the event of a timing chain failure, and supports accurate holdover timing for several hours.

Speaking of telco-friendliness, the AT4848's on-chip redundancy controller allows for graceful failover in high-availability systems. When used in a redundant configuration the standby chip is equipped with several mechanisms to detect a primary failure and an interlock mechanism to prevent conflicts. It has a mechanism to allow the active chip to hand off control in the event of hot-swap or detected failure. Another feature carrier-class equipment designers will like is the monitor channel that provides BER monitoring and alarm processing for all SONET, DS-1s and DS-0's in use.

All these features make the AT4848 a good core element to build the kinds of multi-service, multi-technology access products being built by Calix and Entrisphere as well as micro-MSPP boxes that sit closer to residential and SoHo customers.

As one would expect with a framer/mapper this large, it will draw a significant chunk of power. With the device in the later parts of the design phase, its estimated power consumption stands at 7 W - 9 W, depending on how its used.

While the specs are impressive, the question remains as to whether an upstart like Arrive can actually pull off such a complex design as its first project. Of course such things are possible since I've seen small companies like EZ-Chip, Parama, and Switchcore successfully bring equally ambitious designs to market. Of course, EZ-Chip was six or more months late to market (as I predicted) and Switchcore's Gigabit Ethernet switch required several spins (and over a year) to get its layer-3 processing working properly.

But Arrive has done several smart things that should enhance their odds for success, and keep my skepticism at a low boil. For one thing they have a HUGE overseas engineering team: 70 highly-motivated Vietnamese design engineers managed by one of company's Vietnamese founders. They were also smart enough to not put all their faith in simulation and devoted significant resources to implementing the entire chip in a reduced-speed hardware prototype using Altera FPGAs. And, because the chip was so complex, they were also obliged to supplement their off-the-shelf test equipment with a home-built stimulus generator. Having enough (well-trained) bodies and a hardware-based design verification program provides enough risk reduction that I think they should have useable alpha silicon in one or two spins, and probably within three or four months of their projected sampling date. All this uncertainty adds a half-saltshaker to the AT4848's Vapor Index Rating, but it still remains (just) within the realm of credibility at three saltshakers.

The other question one must ask about an upstart company with only one product is whether they can they create an ecology of reference designs, partnerships with other chip makers, third-party software support, and other elements required to penetrate a difficult market. While my conversations with Mr. Eames were very open about technical details of his chip, he was much less forthcoming about their plans to partner with an Ethernet PHY manufacturer, let alone insinuate themselves into the ecology of an existing supply chain. Only time will tell if they have this part of their business plan properly addressed. I certainly hope they do since it would be sad to see so much effort go to waste.

On the bright side, Arrive is certainly doing its best to make it easy for engineers to evaluate and design with their monster chip. They are almost done preparing a reference design/evaluation kit that's a complete functioning MSPP. It uses PC-based configuration and development tools to customize, or completely re-configure the chip's programmable elements.

The AT4848 is still in tape-out (or whatever they call it these days) and is expected back from the fab between September & October 2005. Sampling is currently scheduled for Q4 of 2005 although a slip to early 2006 would not surprise me. The AT484 is targeted at under $300 in production volumes.

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