Arrive’s Pseudowire CodeChip product line offers a family of complete pseudowire and mobile backhaul CodeChip devices. Arrive provides total solutions in groupings of 1 to 16 DS1/E1/J1 or 1 to 32 DS1/E1/J1 lines; aggregation nodes with up to 84/63 DS1/E1 lines; high-density nodes with 336/252 DS1/E1 lines; or very dense nodes with 1344/1008 DS1/E1/J1 lines. The aggregation and higher density nodes use SONET/SDH interfaces for service side connection.

The Pseudowire CodeChip family begins with a series of core features. From these, each specific design is tailored to a customer’s specifications.

Pseudowire CodeChips

16E1/DS1

  • Supports DS1/E1 pseudowires over packet switched network (SAToP/CESoPSN), ATM pseudowire and packet pseudowire as per RFC4553 and RFC5086
  • Supports up to 128 pseudowire connections
  • Up to 16 serial DS1/E1/J1 interfaces with integrated framer
  • 1xGbE interface (FE optional)
  • IMA/ATM and/or HDLC/PPP/MLPPP support
  • Timing modes for DS1/E1 include: ACR/DCR, external reference, looptime
  • ACR/DCR clock recovery algorithm for SAToP and CESoPSN, meets ITU G.8261, G.823, G.824 and MEF22
  • Very low-cost DDR2/3 for large buffers
  • Application specific high-level API software driver

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32E1/DS1

  • Supports DS1/E1 pseudowires over packet switched network (SAToP/CESoPSN), ATM pseudowire and packet pseudowire as per RFC4553 and RFC5086
  • Supports up to 128 pseudowire connections
  • Up to 32 serial DS1/E1/J1 interfaces with integrated framer
  • 2xGbE interface: one active and one standby
  • IMA/ATM and/or HDLC/PPP/MLPPP support
  • Timing modes for DS1/E1 include: ACR/DCR, external reference, looptime
  • ACR/DCR clock recovery algorithm for SAToP and CESoPSN, meets ITU G.8261, G.823, G.824 and MEF22
  • Very low-cost DDR2/3 for large buffers
  • Application specific high-level API software driver

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STM-4/OC-12

  • PDH pseudowire (SAToP and CESoPSN) and SONET/SDH pseudowire (CEP) as per RFC4553, RFC5086, RFC4842, etc
  • DS1, E1, J1, DS3, E3, with optional M13/E13
  • CEP modes include: VC11, VC12, VC-3 (Basic and Fractional), VC-4 (Basic and Fractional)
  • Supports up to 1024 Pseudowire connections
  • 1xOC12/STM-4 or 4xOC-3/STM-1 interfaces at service side
  • DS1, E1, J1, DS3, E3, with optional M13/E13
  • 2xGbE interface: One active and one standby
  • IMA/ATM and/or HDLC/PPP/MLPPP optional
  • Timing modes for DS1/E1 include: ACR/DCR, external reference, looptime
  • ACR/DCR clock recovery algorithm for SAToP and CESoPSN, meets ITU G.8261, G.823, G.824 and MEF22
  • APM and EPAR Timing modes for CEP
  • Very low-cost DDR2/3 for large buffers
  • Application specific high-level API software driver

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CodeChip SDK

  • Platform independent via a Hardware Abstraction Layer (HAL) module
  • Operating System independent via Operating System Abstraction Layer (OSAL) module
  • Modular oriented device driver allowing transparent interface to higher level application layer
  • Intended to relieve the system software developer of the task of recreating the CodeChip device driver to speed up the system development and ensure a quick transition to production
  • Compliant to standard telecommunications functions including configuration
  • Supports interrupt handler
  • Includes a command line debugger for controlling and monitoring the device
  • Compliant to ANSI-C