Arrive’s Carrier Ethernet CodeChip® product line offers a family of complete Ethernet switch, Carrier Ethernet, mobile backhaul, broadband access and packet optical transport CodeChip devices. Arrive provides total solutions in groupings of 2 to 8 GbE ports; up to 16 FE ports; aggregation nodes with up to 24 GbE ports; 10G uplinks with 2 10GbE ports and high-capacity nodes with up to multiple 10GbE ports.

CodeChips provide a software programmability of UNI and NNI for each port. Optical fibers are provided with integrated transceivers inside FPGAs, none of external component required. Twisted pair cables are provided with external PHYs. For service providers’ requirements, CodeChips provide Non-blocking packet switching, MPLS-TP, OAM, ACL, SLA, Statistic Counts, QoS and Ring in hardware implementation. For system requirement, CodeChips provide Redundancy, Timing and Service Activation Test in hardware implementation. Timing is provided as 1588v2 time-stamping, transaction, algorithm and a combination with Sync-E and Stratum 3E clock synthesizer. As applications require circuit emulation service, CodeChips provide 16xE1/T1 ports integrated or a companion with Pseudowire CodeChip family

CodeChips are provided with CodeChip API as a single API software driver for all CodeChip variants. CodeChip API supports protocol stack handling. For customers who want to re-use their investment on existing software, Arrive supports migration from customer’s existing software to re-use it with CodeChip solutions.

The Carrier Ethernet CodeChip family begins with a series of core features. From these, each specific design is tailored to a customer’s specifications.

Arrive is currently developing a new family of Next Generation CodeChips. This new family will add SDN-Ready capabilities to Arrive’s CodeChip products*. This new capability will be known as FreeFlo™.

Carrier Ethernet CodeChips

CE8

  • Supports 8 GbE ports
  • Supports Ethernet Switch, Carrier Ethernet Switch, MPLS-TP Switch among FE, GbE and 2.5GbE ports
  • Provides up 16xE1/T1 ports integrated for Circuit Emulation applications or a companion with Pseudowire CodeChip family
  • Single application specific high-level API software driver for all CodeChip variants. Supports protocol stack handling
  • Supports migration from customer’s existing software to re-use it with CodeChip solutions
  • Provides a software programmability of UNI and NNI for each ports
  • Provides optical fiber interface with integrated transceivers inside FPGA. No external component required
  • Provides twisted pair cable interface with external PHYs. Supports all PHY standard interfaces
  • Supports system backplanes and chip-to-chip interfaces: 10GBase-KR, XAUI, G.999.1 and others
  • Service Provider’s features: Non-blocking packet switching, MPLS-TP, OAM, ACL, SLA, Statistic Counts, QoS and Ring in hardware implementation
  • System features: Redundancy, Timing and Service Activation Test in hardware implementation
  • Timing features: 1588v2 time-stamping, transaction, algorithm and a combination with Sync-E and Stratum 3E clock synthesizer
  • Very low-cost DDR3 for large buffers

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CE24

  • Supports 24 GbE ports
  • Supports Ethernet Switch, Carrier Ethernet Switch, MPLS-TP Switch among FE, GbE and 2.5GbE ports
  • Provides up 16xE1/T1 ports integrated for Circuit Emulation applications or a companion with Pseudowire CodeChip family
  • Single application specific high-level API software driver for all CodeChip variants. Supports protocol stack handling
  • Supports migration from customer’s existing software to re-use it with CodeChip solutions
  • Provides a software programmability of UNI and NNI for each ports
  • Provides optical fiber interface with integrated transceivers inside FPGA. No external component required
  • Provides twisted pair cable interface with external PHYs. Supports all PHY standard interfaces
  • Supports system backplanes and chip-to-chip interfaces: 10GBase-KR, XAUI, G.999.1 and others
  • Service Provider’s features: Non-blocking packet switching, MPLS-TP, OAM, ACL, SLA, Statistic Counts, QoS and Ring in hardware implementation
  • System features: Redundancy, Timing and Service Activation Test in hardware implementation
  • Timing features: 1588v2 time-stamping, transaction, algorithm and a combination with Sync-E and Stratum 3E clock synthesizer
  • Very low-cost DDR3 for large buffers

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CE32

  • Supports 2 10GbEports and 12 GbE ports
  • Supports Ethernet Switch, Carrier Ethernet Switch, MPLS-TP Switch among FE, GbE, 2.5GbE and 10GbE ports
  • Provides up 16xE1/T1 ports integrated for Circuit Emulation applications or a companion with Pseudowire CodeChip family
  • Single application specific high-level API software driver for all CodeChip variants. Supports protocol stack handling
  • Supports migration from customer’s existing software to re-use it with CodeChip solutions
  • Provides a software programmability of UNI and NNI for each ports
  • Provides optical fiber interface with integrated transceivers inside FPGA. No external component required
  • Provides twisted pair cable interface with external PHYs. Supports all PHY standard interfaces
  • Supports system backplanes and chip-to-chip interfaces: 10GBase-KR, XAUI, G.999.1 and others
  • Service Provider’s features: Non-blocking packet switching, MPLS-TP, OAM, ACL, SLA, Statistic Counts, QoS and Ring in hardware implementation
  • System features: Redundancy, Timing and Service Activation Test in hardware implementation
  • Timing features: 1588v2 time-stamping, transaction, algorithm and a combination with Sync-E and Stratum 3E clock synthesizer
  • Very low-cost DDR3 for large buffers

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CE50

  • Supports Ethernet Switch, Carrier Ethernet Switch, MPLS-TP Switch among GbE, 2.5GbE and 10GbE ports
  • Provides up 16xE1/T1 ports integrated for Circuit Emulation applications or a companion with Pseudowire CodeChip family
  • Single application specific high-level API software driver for all CodeChip variants. Supports protocol stack handling
  • Supports migration from customer’s existing software to re-use it with CodeChip solutions
  • Provides a software programmability of UNI and NNI for each ports
  • Provides optical fiber interface with integrated transceivers inside FPGA. No external component required
  • Provides twisted pair cable interface with external PHYs. Supports all PHY standard interfaces
  • Supports system backplanes and chip-to-chip interfaces: 10GBase-KR, XAUI, G.999.1 and others
  • Service Provider’s features: Non-blocking packet switching, MPLS-TP, OAM, ACL, SLA, Statistic Counts, QoS and Ring in hardware implementation
  • System features: Redundancy, Timing and Service Activation Test in hardware implementation
  • Timing features: 1588v2 time-stamping, transaction, algorithm and a combination with Sync-E and Stratum 3E clock synthesizer
  • Very low-cost DDR3 for large buffers

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CE100

  • Supports Ethernet Switch, Carrier Ethernet Switch, MPLS-TP Switch among GbE, 2.5GbE and 10GbE ports
  • Provides up 16xE1/T1 ports integrated for Circuit Emulation applications or a companion with Pseudowire CodeChip family
  • Single application specific high-level API software driver for all CodeChip variants. Supports protocol stack handling
  • Supports migration from customer’s existing software to re-use it with CodeChip solutions
  • Provides a software programmability of UNI and NNI for each ports
  • Provides optical fiber interface with integrated transceivers inside FPGA. No external component required
  • Provides twisted pair cable interface with external PHYs. Supports all PHY standard interfaces
  • Supports system backplanes and chip-to-chip interfaces: 10GBase-KR, XAUI, G.999.1 and others
  • Service Provider’s features: Non-blocking packet switching, MPLS-TP, OAM, ACL, SLA, Statistic Counts, QoS and Ring in hardware implementation
  • System features: Redundancy, Timing and Service Activation Test in hardware implementation
  • Timing features: 1588v2 time-stamping, transaction, algorithm and a combination with Sync-E and Stratum 3E clock synthesizer
  • Very low-cost DDR3 for large buffers

Learn More

CodeChip SDK

  • Single application specific high-level API software driver for all CodeChip variants. Supports protocol stack handling
  • Supports migration from customer’s existing software to re-use it with CodeChip solutions
  • Platform independent via a Hardware Abstraction Layer (HAL) module
  • Operating System independent via Operating System Abstraction Layer (OSAL) module
  • Modular oriented device driver allowing transparent interface to higher level application layer
  • Intended to relieve the system software developer of the task of recreating the CodeChip device driver to speed up the system development and ensure a quick transition to production
  • Compliant to standard telecommunications functions including configuration
  • Supports interrupt handler
  • Includes a command line debugger for controlling and monitoring the device
  • Compliant to ANSI-C